Abstract:

This thesis presents a probabilistic classification method for the recognition of walking behaviors. The widely used method of Hidden Markov Models is combined with a Code Book Quantizer to adapt to the new context of continuous pedestrian motion classification. The implemented system improves the functionality of indoor navigation systems and correct position error estimates, by providing additional context information. Using the foot-mounted unit of the PiNav-System, designed at the Institute for Real-Time Computer Systems (RCS), measurement data of walking behaviors are gathered from inertial measurement sensors, basically an accelerometer and a gyroscope. Processing raw data to assess characteristic information of walking behaviors, extracting significant streams as well as modeling, training and recognizing proceeded motions, are the main key issues in such systems and will be discussed in depth.

Abstract:

Wireless sensor networks (WSN) are gaining popularity in part due to their high relia- bility, dynamic reconfigurability, low cost and ability to measure and analyze distributed sources. Examples include environmental monitoring, sound (object) localization or ac- tivity detection in form of body area networks (BAN). For the latter application large quantities of acceleration data are processed and transmitted to collection devices which can result in substantial power expenditures from wireless communication alone. Data compression on the sensing nodes could be used to reduce the amount of transmitted data as long as activity detection is not compromised. The activity analysis algorithm used with an existing multi-sensor mote was revised and optimized for low-complexity hard- ware without compromising its sensitivity. Then selected data compression methods were evaluated against this algorithm. Slepian-Wolf Coding and run-length encoding were not effective in compressing acceleration data while differential encoding, a dictionary method and foremost wavelet based compression were highly effective. A multistage compression algorithm (wavelet filtering, differential encoding, exponential Golomb code) was derived from these analyses. Finally a new BAN mote with typical limited processing power and storage capability was designed and the components of the proposed compression scheme implemented to demonstrate feasibility and measure the current consumption. Differential encoding with a variable length code resulted in a ca. 45% increase in power consumption as the increase in computation (largely due to inefficiently implemented bit manipula- tions) exceeded the decrease in communication. Wavelet filtering to 25% of the original data rate resulted in a ca. 17% decrease in power consumption exclusively due to the reduction in communication while the expense of computation was nearly unaltered.

Abstract:

Numerous driver assistance systems require information about the vehicle's surroundings. Robust vehicle environment perception, which is necessary for applications such as highly automated and autonomous driver assistance system, is guaranteed by asynchronous sensors with complementary features and overlapping field of views. This thesis is about the investigation and development of algorithms and approaches for track-to-track fusion within a high-level sensor data fusion architecture for highly automated driving applications. Algorithms which are already known in the literature are studied within a simulation environment to evaluate the quality of their results and usability in practical applications. Additionally, these algorithms are adapted to the automotive environment and the most promising algorithm is integrated into an architecture within a vehicle in order to evaluate the developed fusion concept using real sensor data. The goal of this thesis is to enable 360 surround environment perception and tracking using an underlying diverse sensor configuration.

Abstract:

An admission control test is required for a real-time system to decide whether an incoming task could be accepted while the system already has a set of running tasks, so that the whole tasks set including the new one is feasible. For online real-time systems the admission control decisions are to be taken on-line, and, of course, as accurate as possible. There are already many algorithms introduced to fulfill those requirements. In this paper we focus on improvements on admission control tests which were introduced by Dr. Alejandro Masrur, Prof. Samarjit Chakraborty and Dr. Georg Faerber in the year 2010 and 2011 for tasks scheduled on identical processors under partitioned Earliest Deadline First (EDF) and for tasks scheduled under partitioned Deadline Monotonic (DM). We assume the tasks in the case have constraint-deadlines, which means that the relative deadlines of each job may be less than the minimum separation between two consecutive task activations or jobs ( in short tasks with deadlines smaller or equals to their periods ). While the proposed test for DM policy in the publication in 2011 seems to be near-optimal" for tasks set with random tasks and is also the updated of the test proposed in the publication in 2010 for EDF policy, those tests could still be improved more, as described later in this paper. And these tests with improvements are tests with the highest accuracy/complexity ratio we know so far. We evaluate the improvements with the original proposed tests and with other tests with high complexities and the tests with highest accuracies. We use Matlab for the simulations."

Abstract:

Kameras in Outdoor- und insbesondere Automotive-Umgebungen werden mit einem sehr hohen Dynamikumfang an einfallenden Lichthelligkeiten konfrontiert. Die meisten CMOS-Kameras können diesen Dynamikumfang nicht abbilden - sehr helle Bildbereiche sättigen und sehr dunkle Bildbereiche werden unterbelichtet. Spezielle HDR-Kameras erreichen durch die Schaltungen in ihren Pixeln stückweise lineare Kennlinien und können damit den darstellbaren Dynamikumfang erweitern. Diese Diplomarbeit befasst ich damit, wie eine solche HDR-Kamera verwendet werden kann, um in Automotive und Outdoor-Applikationen eingesetzt zu werden. Aufgrund der Nichtlinearitäten in der Kamerakennlinie besitzen die generierten Bilder solcher Kameras einen nichtlinearen Zusammenhang zwischen einfallenden Lichthelligkeiten und den zugehörigen Grauwerten. Diese Diplomarbeit stellt eine Modellierung der Kamera vor, mit deren Hilfe die Bilddaten linearisiert werden können. Außerdem wird eine erweiterte Belichtungsregelung vorgestellt. Zudem wird beschrieben, wie ein Satz an geeigneten Kameraparametern für den Einsatz der Kamera im Automotive-Umfeld gefunden werden kann.

Abstract:

Design of time critical embedded systems is usually based on the theory of real-time systems. While such theory is sound, the implementation of such systems on speculative processors leads to many possibilities of errors. In this talk, we propose an alternative approach based on Precision Timed (PRET) architectures. PRET architectures guarantee precise timing without sacrificing throughput. I will focus on a recent synchronous C variant called PRET-C for programming PRET architectures. We map logical time in PRET-C to physical time using static timing analysis. Benchmarking results show that the proposed approach provides a scalable and efficient mechanism for realizing precision timed systems.

Biography:

Partha is a Senior Lecturer and is currently the Program Director of the Computer system Engineering program. His research interests are in the area of Embedded Systems, Real-Time systems and static timing analysis. He is particularly interested in static analysis techniques for validation, safety and certification. Partha is an Associate Editor of Elsevier Journal on Embedded Hardware design (MICPRO) and EURASIP Journal on Embedded Systems. In 2009, he received the Alexander von Humboldt fellowship for experienced researchers from the Humboldt foundation, Germany and worked with Prof. Reinhard von Hanxleden of CAU, Kiel.

Abstract:

Concepts of control theory and real-time systems are gradually getting intertwined as control applications are increasingly scheduled over networked system of ECUs connected by a buses. In this context, evaluating control performance and evaluating system resources are still being treated as two individual topics. Through our current work, we attempt to bridge this gap and evaluate control performance and extensibility from a co-design perspective. Towards this, we concretize the notions of extensibility for the ECUs and the bus. In particular, we constructively build three approaches for measuring the extensibility of an ECU under a time-triggered and non-preemptive task model. We then study the variations in control performance and component extensibilities by scheduling a new control application on an existing system of ECUs interconnected by a FlexRay based bus. Our experimental results indicate that for a given period of control application one can

Abstract:

Texas Instrument's MSP430 micro-controllers are optimized for ultra low power applications through their different low power operation modes. They have several power states with different power consumptions adjusted to different operation modes. Accurately determining how much power is being drawn by the micro-controller and its peripherals in different power states, requires a precise dynamic system, which can keep track of the real-time power consumption of the micro-controller. In this thesis a profiling solution was developed to sense the current consumption of MSP430 micro-controllers. The goal was to sense currents ranging from 0,1µA to 100mA with a measurement bandwidth of 10kHz and a budget limitation of 7$ in terms of bill of material. The current profiling circuit was intended to be integrated into the debugging interface and to be usable for all MSP430 generations. The circuit implemented in this thesis is based on resistive current sensing. It consists of a shunt resistor within the supply line of the MSP430 and a unit measuring the voltage drop across it. Simulation data in combination with measurement results have shown a trade-of between the measurement bandwidth and the lowest current that can be sensed: the higher the bandwidth, the more difficult it becomes to sense very tiny currents and vice versa. The designed circuit is capable of measuring currents in the range of 1µA to 50µA with a maximum bandwidth of 5kHz and currents ranging from 50µA to 100mA with a dynamic of 8kHz

Abstract:

In this bachelor thesis, we developed a new vision system for the Robosoccer lab at the RCS. Instead of the white markers, markers with different colors are used now to distinguish the robots from each other. Therefore we implemented a color-based classification to recognize the robots. Unlike the old vision system, where the robots and the ball are searched in the entire image, in the new algorithm we predict the positions of the objects and only search the image in small areas around these predicted positions. This contributed considerabely in reducing the processing time compared to the old vision system. As a last part of this project a kalman filter is used to reduce the effect of the camera noise on the determination of the robot's and ball's position.

Abstract:

Ethernet has emerged to be the de-facto standard for local area networks. In this thesis we will discuss the task of fragmentation for PROFINET, an Ethernet based real-time bus system for industrial automation applications. The real-time capabilities of PROFINET are based on a bandwidth splitting approach via TDMA. In order to improve the achievable TDMA cycle-time the maximum transmission unit must be reduced. This is done transparently by fragmentation while keeping compatibility to legacy Ethernet devices. In this thesis multiple PROFINET compatible fragmentation algorithms were developed and compared. On the other hand, the influence of the maximum transmission unit to the delay of real-time traffic was analyzed. Thereby contradicting requirements during the delay and bandwidth optimization were found. Finally, we combined these insights and found a compromise improving the delay and jitter of delay sensitive traffic while keeping the performance of bandwidth sensitive traffic more or less equal. The analytical results were deduced from a simple PROFINET model which was verified using a SystemC event simulation.

Abstract:

Without proper GPS signals, indoor navigation is still an ongoing research topic. As part of the PiNav Project, this thesis's target is to improve the the localization quality of the system. First, a new sensor box is programed that is equipped with more precise inertial sensors than the old one, so that the dead reckoning system can operate on a more accurate data basis. Second, a magnetic map is implemented that allows incorporation of absolute position information into the algorithm. Additionally, a novel mapping algorithm is presented, that is specially designed for the needs of the current system. Namely this means only a rough position estimation and limited processing power.

Abstract:

Despite the numerous benefits offered by 3D integration, testing remains a major obstacle that hinders its widespread adoption. Test techniques and design-for-testability (DfT) solutions for 3D ICs have remained largely unexplored in the research community, even though experts in industry have identified a number of test challenges related to the lack of probe access for wafers, test access to modules in stacked wafers/dies, thermal concerns, test economics, and new defects arising from unique processing steps such as wafer thinning, alignment, and bonding. In this talk, the speaker will present a number of testing and DfT challenges, and some of the solutions being advocated for these challenges. The speaker will focus on pre-bond TSV testing, DfT innovations related to the optimization of die wrappers, test scheduling, and access to dies and inter-die interconnects during post-bond (stack) testing.

Biography:

Krishnendu Chakrabarty received the B. Tech. degree from the Indian Institute of Technology, Kharagpur, in 1990, and the M.S.E. and Ph.D. degrees from the University of Michigan, Ann Arbor, in 1992 and 1995, respectively. He is now Professor of Electrical and Computer Engineering at Duke University. He is also a Chair Professor in Software Theory at Tsinghua University, Beijing, China. Prof. Chakrabarty is a recipient of the National Science Foundation Early Faculty (CAREER) award, the Office of Naval Research Young Investigator award, the Humboldt Research Fellowship from the Alexander von Humboldt Foundation, Germany, and several best papers awards at IEEE conferences. Prof. Chakrabarty's current research projects include: testing and design-for-testability of integrated circuits; digital microfluidics, biochips, and cyberphysical systems; optimization of digital print and production system infrastructure. He has authored 10 books on these topics (with two more books in press), published over 370 papers in journals and refereed conference proceedings, and given over 150 invited, keynote, and plenary talks. Prof. Chakrabarty is a Fellow of IEEE, a Golden Core Member of the IEEE Computer Society, and a Distinguished Engineer of ACM. He was a 2009 Invitational Fellow of the Japan Society for the Promotion of Science (JSPS). He is a recipient of the 2008 Duke University Graduate School Dean???s Award for excellence in mentoring, and the 2010 Capers and Marion McDonald Award for Excellence in Mentoring and Advising, Pratt School of Engineering, Duke University. He served as a Distinguished Visitor of the IEEE Computer Society during 2005-2007, and as a Distinguished Lecturer of the IEEE Circuits and Systems Society during 2006-2007. Currently he serves as an ACM Distinguished Speaker, as well as a Distinguished Visitor of the IEEE Computer Society for 2010-2012.

Abstract:

Network calculus is a theory based on the (min,plus) algebra for computing deterministic performance guaranties in networks. In this talk, I will deal with two problems related to Network calculus. 1) the tighness issue: the algebraic framework enables to easily combine network elements, and the algorithmic cost of this is very low. But the bounds that are computed may be very high compared to the actual worst case performances. We show under some assumptions how to compute the worst-case delays using linear programming. We also show that the problem is NP-hard. 2) optimisation issue: We solve the following simple problem. Given one flow and one network, what is the path going to one source to one destination that guaranties the shortest end-to-end delay.

Biography:

Dr. Anne Bouillard is an assistant professor at ENS Paris since September 2010, working in Francois Baccelli's group. Before that she was at ENS Cachan (since 2006). She also studied at ENS and obtained her PhD from ENS Lyon in 2005, followed by a postdoctoral stay at the National Tsing Hua University of Taiwan in 2006.

Abstract:

How will industrial automation technology benefit from multi-core and many-core architectures? At Siemens Corporate Research we are actively solving the problems faced when shifting the technology that enforces sequential execution to parallel processing. The computation paradigm for Industrial Automation applications must guarantee, by all means, deterministic behavior and real-time response. These constraints have a negative impact when optimizing and parallelizing these workloads. We present a novel idea that might help to exploit untapped synchronous task parallelism. The key observation is that at the functional level, Industrial Automation programming languages (e.g. IEC 61131) can be characterized as a multi-rate synchronous dataflow optimization problem that can be sliced, load-balanced, and scheduled into multiple processing units. We will review the basics of PLC technology, motivate the use of parallel computing, and review the code transformations introduced by our algorithms.

Biography:

Arquimedes Canedo is a Research Scientist at Siemens Corporate Research. He received a Dr.Eng. from the University of Electro-Communications in Tokyo, Japan. He worked as a Researcher at IBM Research - Tokyo where he developed the first auto-parallelization algorithms for Simulink. His research interests are high-performance computing, simulation, synchronous programming languages, and cyber-physical systems.

Abstract:

Multicore processors have become a central pillar in real-time embedded systems. In the last ten years this was mainly confined to academic work, but now industrial adoption is in full steam. This is underpinned by activities like the Artemis RECOMP project, which aims to reduce the cost of certification for multicore based systems with mixed criticality workload. the latter describes a mix of critical and uncritical applications in a single device. Within this talk, I will present current activities and results at the CISTER research unit at the Engineering School of the Polytechnic Institute of Porto discussing various angles of such systems. Energy Management in this context relates to the use of dynamic frequency and voltage switching, as well as dynamic use of sleep states. One particular problem in the deployment of multicores is the access to main memory which is ultimately subject to contention by the different cores. Analytical models to bound the impact of the bus activity of applications running on other cores are key to guarantee real-time behaviour. Finally many such systems are subject to different operating modes. An illustrative example are planes, which require different sets of task to execute taxiing, starting, landing and in cruise mode.

Biography:

Dr. Stefan M. Petters is an alumnus of the Institute of Real-Time Computing Systems at the Technical University of Munich. He received his Dipl.-Ing. degree in 1995 from TUM with a Diplomarbeit in the area of Task-Allocation in Distributed Real-Time Systems using evolutionary algorithms. In 2002 he received the Dr.-Ing. in 2002 with his thesis of ''Worst Case Execution Time Estimation for Advanced Processor Architectures'' under the supervision of Prof. Gerorg Färber. Since completing his degree, he has worked in various prominent research groups. This covers the Real-Time systems group at the University of York, UK, where he continued his work on WCET analysis. In 2004 Stefan moved to the ERTOS group at NICTA, in Sydney Australia. The group his world leading in the operating systems area and he worked in the group on WCET analysis of microkernels, as well as power management of embedded platforms. In 2009 Stefan moved to the CISTER research unit at the Polytechnic Institute of Porto, where he acts as vice-director of the unit and research-line leader for adaptive real-time systems. He continues his work on power management, and low level timing analysis in open real-time systems.

Abstract:

Im Rahmen der Ingenieurspraxis wurde eine Testsoftware mit graphischer Benutzeroberfläche entwickelt. Die Testsoftware ermöglicht das automatische Testen neuer Embedded Computer Modules bezüglich ihrer Betriebsstabilität. Mit Hilfe der Testsoftware kann, durch verschiedene Tests, die Betriebsstabilität bei langsamen Einschaltvorgängen und Spannungsschwankungen überprüft werden. Weiterhin können die Tests bei verschiedenen Umgebungstemperaturen durchgeführt werden. Im Vortrag werden verschiedene Testaufbauten vorgestellt und deren Testablauf erklärt. Anschließend wird kurz auf die Schritte der programmtechnischen Umsetzung eingegangen und die Funktion der Testsoftware erläutert.

Abstract:

Range estimation in battery vehicles - Air conditioning consumption: This student research introduces a method for estimating future power consumption by an air conditioning system. It is designed for the upcoming BMW Megacity Vehicle (MCV), a car designed for urban scenarios using only battery power. The model was realized in MATLAB/Simulink, based on thermal simulations using Dymola. It delivers two main output signals: a constant power, which is used to keep the reached interior target temperature, and an additional energy to reach this level. The calculation is based on customer settings, environmental influences and car-/ac-controller specifics. It is also designed to be reusable for future cars. Additionally the extra energy consumption for cooling the high voltage battery was covered, which has to stay beneath a specific temperature.

Abstract:

When locking protocols are used in real-time systems, bounds on blocking times are required when ensuring timing constraints. While the term blocking" is well-understood in the context of uniprocessor real-time systems, the same is not true in the multiprocessor case. In this talk, two definitions of blocking are presented that are applicable to suspension-based multiprocessor locking protocols. The need for two definitions arises because of differences in how suspensions are handled in existing schedulability analysis. For each definition, locking protocols are presented that have asymptotically optimal blocking behavior. In particular, protocols are presented for any job-level static-priority global or partitioned scheduling algorithm. "

Biography:

Björn Brandenburg is a graduate student in the Department of Computer Science at the University of North Carolina at Chapel Hill (UNC). He received his undergraduate education from the Technische Universität Berlin and transferred to UNC on a Fulbright Fellowship in 2006. He received an M.S. degree in Computer Science from UNC in 2008 and expects to defend his dissertation in August 2011. His research interests include multiprocessor real-time system, real-time synchronization protocols, and operating systems.

Abstract:

Die zunehmenden Auswirkungen des Klimawandels erfordern eine effiziente und nachhaltige Begrenzung der Auswirkungen der Luftfahrt auf die Umwelt. Im Gegensatz dazu stehen die prognostizierten langfristig stark ansteigenden Passagierzahlen. Um sowohl der erhöhten Transportleistung als auch den umweltpolitischen Zielen gerecht werden zu können, müssen neue Technologien für das Design und die Herstellung von Flugzeugstrukturen entwickelt werden. Dabei fällt ein großer Anteil auf faserverstärkte Kunststoffe, die jedoch noch nicht in großen Stückzahlen rationell zu verarbeiten sind.

Diese Arbeit ist Teil eines LUFO-IV Projektes namens ProFIT. In dem Förderprojekt soll eine automatisierte intelligente Tow Placement Anlage zur Ablage von endlosfaserverstärkten Halbzeugen in einer durchgängigen Prozesskette realisiert werden. Zur Ablage der Halbzeuge wird ein Industrieroboter eingesetzt der offline auf Grundlage von CAD-Daten programmiert werden soll. Zwischen den Faserhalbzeugen dürfen keine Lücken entstehen. Da verschiedene Ungenauigkeiten bei der Positionierung und durch die Werkzeugfertigung auftreten, müssen verschiedene Sensoren eingesetzt werden um diese auszugleichen und der Entstehung von Lücken entgegen zu wirken.

In dieser Arbeit wird ein Anlagenkonzept erstellt. Das Augenmerk wird dabei vor allem auf den Steuerungsrechner gerichtet. Der Rechner wird auf Linuxbasis arbeiten. Um den Echtzeitanforderungen des Industrieroboters nachzukommen wird das Betriebssystem mit RTAI erweitert. Zur Interprozesskommunikation wird Kogmo-RTDB eingesetzt und zur Ethernet-Kommunikation RTnet. Es wurde außerdem versucht die Qualität der Echtzeitfähigkeit anhand von Versuchen nachzuweisen.

Abstract:

In recent times, a new in-vehicle communication protocol, FlexRay, has emerged to become a de-facto standard for automobile communication systems. In this thesis, the model-based development steps of distributed control applications on FlexRay networks are discussed. Network design considerations related to control stability are discussed.

Abstract:

Embedded systems are a new focal point of computer engineering. Typical examples include automotive systems, complex sensor networks, cyber-physical systems, manufacturing and control systems, robotics, intelligent home and office environments etc. For their complexity, particularly their interaction with the physical world on one end and computer execution platform on the other, which often involves real-time requirements, they raise many new challenges such as determinism in reactions to external events, real-time operation, robustness and reliability, scalability and execution platform resource awareness, which are not typical for traditional best-effort computing.

Systematic approach to embedded systems engineering will be the key for their successful deployment in variety of application areas. We argue that the design approaches based on formal models of computation, are potentially the answer to deal with the challenges engineers face. The design approach centred on a formal model of computation (MoC) gives the opportunity to check for the properties of the designed system at various levels of abstraction the systems are presented during their design, deal will well defined system model that may lead towards correct by construction systems and formalize and automate the whole design flow.

As an example of a formal MoC we use and propose is the globally asynchronous locally synchronous (GALS) model that naturally models huge number of embedded systems, provides for modelling of interaction of the designed system with the physical world and is scalable in its both versions, static and dynamic GALS. It also represents a natural link between the physical systems and computer execution platform on which an embedded system is implemented. This model was used as the main inspiration for proposing and implementing two new system-level design (and programming) languages, SystemJ and DSystemJ, for static and dynamic systems design, respectively. Those two languages and their execution will be presented in more details. We will also discuss the execution platform challenges and the outlook of extending those languages towards satisfying requirements of real-time systems.

Biography:

Zoran Salcic is a professor of computer systems engineering at the University of Auckland. He received the BE (1972), ME (1974), and PhD (1976) degree in electrical engineering from the University of Sarajevo while doing most of his PhD research at the CCNY of the City University of New York (CUNY). He published more than 250 journal and conference papers, books and book chapters, as well as major technical reports in the areas of complex digital systems design, custom-computing machines, reconfigurable systems, FPGAs, processor and computer systems architectures, embedded systems and their implementation, design automation tools for embedded systems, hardware-software co-design, new computing architectures and models of computation for heterogeneous embedded systems. He is a fellow of the Royal Society (Academy of Science) New Zealand. Currently (2010) he is the visiting professor at the Friedrich-Alexander University, Erlangen-Nuremberg, as the recipient of Humboldt research award.

Abstract:

The extreme complexity/energy requirements and context-aware processing nature of next generation multimedia applications stimulate the need for adaptive low-power embedded multimedia systems with high-performance. Run-time adaptivity is required to react to the run-time varying scenarios (e.g., quality and performance constraints, available energy, input data). This talk accentuates the basic shortcomings of state-of-the-art and discusses the emerging trend of dynamically reconfigurable processors along with their energy-related issues, i.e., reconfiguration power, leakage power, and lack of efficient energy management features. Afterwards, novel techniques for adaptive energy management at both processor architecture and application architecture levels are introduced that exploit the available potential of energy reduction in adaptive multimedia systems (based on dynamically reconfigurable processors) while meeting the performance/area constraints and keeping the video quality degradation unnoticeable, under run-time varying scenarios. An emphasis is placed on the fact that power-energy reduction needs to be combated at various abstraction levels. At the processor architecture level the novel concept of Selective Instruction Set Muting is introduced that raises the abstraction level of power-shutdown to the custom instruction set level, i.e., an instruction-set oriented shutdown. It thereby enables a far higher potential for leakage energy savings. A run-time adaptive energy management scheme determines an energy-minimizing instruction set and performs the Selective Instruction Set Muting on the temporarily unused instruction set in order to minimize the overall energy. This talk additionally discusses the application-level adaptivity and energy reduction using an advanced video encoder (like H.264/AVC) that incorporates the novel concept of Energy-Quality Classes, video properties dependent adaptive complexity reduction, and an adaptive energy budgeting scheme to realize the adaptive low-power video encoding. Compared to state-of-the-art, the proposed contribution provides significant energy savings. Altogether, the proposed processor and application architectures enable adaptive embedded multimedia systems with low power/energy consumption to provide means for next-generation mobile multimedia applications and emerging multimedia standards.

Biography:

Muhammad Shafique has a 7+ years' research and development experience in adaptive, low-power, and high-performance embedded multimedia systems in leading industrial and research organizations. He received his B.Sc. Engineering degree with 4 Gold Medals and M.Sc. Information Technology degree with 2 Gold Medals from Pakistan. Since 2006, Mr. Shafique is pursuing his Ph.D. with Prof. Dr. Jörg Henkel, Karlsruhe Institute of Technology (KIT), Germany. His main research interests are extensible processors and reconfigurable computing systems for adaptive low-power embedded multimedia with a focus on concepts that allow systems to dynamically adapt to the run-time changing requirements/situations. Mr. Shafique holds one US patent, DATE'08 Best Paper Award, ICCAD'10 Best Paper Nomination, HiPEAC Paper Award, and Best Master's Thesis Award. He has 20+ research publications in the premier conferences and journals. Mr. Shafique has also served as an external reviewer for various premier conferences and journals (including DAC, ICCAD, DATE, TVLSI, TCSVT, etc.). He is a member of IEEE and ITG/VDE.

Abstract:

The rising density and heterogeneity of field-programmable gate arrays (FPGAs) enable the implementation of complete reconfigurable systems on a single chip. While such reconfigurable systems on chip integrate processor cores, reconfigurable logic cores, fixed-function cores, memories and interconnects, there is still a lack of efficient programming models. Especially reconfigurable logic cores and the feature of partial hardware reconfiguration are not yet sufficiently supported by design methodologies and tools.

In this talk we present ReconOS, an ongoing project that aims at providing a programming model and execution environment for reconfigurable systems on chip. ReconOS bases on the open source operating systems eCos and Linux, and extends the widely-used multithreading programming model across the software/hardware boundary. First, we discuss the novel concept of hardware threads and show their interaction with the operating system. Then, we turn to the ReconOS execution environment which utilizes Xilinx VirtexIIPro and Virtex4 FPGA technology and facilitates partial hardware reconfiguration. Finally, we present performance data and overheads for ReconOS services and report on an object tracking case study.

Biography:

Marco Platzner is Professor for Computer Engineering at the University of Paderborn. Previously, he held research positions at the Computer Engineering and Networks Lab at ETH Zurich, Switzerland, the Computer Systems Lab at Stanford University, USA, the GMD - Research Center for Information Technology (now Fraunhofer IAIS) in Sankt Augustin, Germany, and the Graz University of Technology, Austria. Marco Platzner holds diploma and PhD degrees in Telematics (Graz University of Technology, 1991 and 1996), and a ''Habilitation'' degree for the area hardware-software codesign (ETH Zurich, 2002). His research interests include reconfigurable computing, hardware-software codesign, and parallel architectures.

Abstract:

Rate-monotonic (RM) scheduling dominates real-time applications in the industry because of its simplicity and predictability. In spite of this, for RM schedulability analysis, no algorithm of polynomial complexity has been found. Thus, several only sufficient tests have been proposed. Most of them are based on utilization bounds, i.e., inequalities as closed-form tests. Famous examples are the Liu/Layland test, the Hyperbolic Bound and Burchard's bound. Based on the principle of Accelerated Simply Periodic Task Sets (ASPTSs), an alternative non-closed-form approach, we present new algorithms: Specialization with respect to r (Sr) and Distance-Constrained Tasks (DCT). It will be shown that these algorithms achieve better sensitivities (success rates). The price is a higher computational complexity of O(n log n) or O(n2) which reduces their suitability for online admission control. On the other hand, their parallelization potential is a matter of fact that can compensate this drawback.

Biography:

Mueller, Dirk, Dr.-Ing., Dipl.-Inf.; 1995 High school diploma (Abitur) with deepened mathematical-scientific education at Johannes-Kepler-Gymnasium Chemnitz; Studies of Medical Informatics at University of Leipzig including 2 semesters abroad studies at Mid Sweden University in Sundsvall in Sweden. 2006 Graduation to Dr.-Ing., dissertation ''Sub-pixel filtering for an autostereoscopic multi-perspective 3-D representation of high quality'' in informatics at University of Kassel. 2006-08 Research Associate at Philipps-University of Marburg with topics Idea of Man and IT as well as Model-driven Software Develpoment. In winter term 2007/08 lecturer at University of Applied Sciences Fulda, lecture ''Formal Methods of Software Engineering''. Since 2008 Assistant Professor (Akademischer Rat) at TU Chemnitz, Operating Systems Group. In winter terms 2009/10 and 2010/11 own lecture ''Design of Software for Embedded Systems.''

Abstract:

In recent times, a new communication protocol, FleyRay, has emerged to become a de-facto standard for automobile communication systems. In this thesis we will discuss the model-based development of distibuted controllers on FlexRay networks. We will discuss the network design considerations related to control stability. The study first indicates several key components related to the time delay through an analysis of the FlexRay network protocol and presents design guidlines for choosing the network and controller parameters in distributed control systems.

Goals of the thesis:
- Understanding the FlexRay communication protocol
- Model-based software development using Matlab/Simulink/Simtools/EB-Hardware
- Implementation of distributed controllers on a FlexRay bus
- Analysis of system stability
- Design constraints/guidelines for FlexRay network parameter design
- Experimental case studies

Abstract:

Diese Bachelorarbeit beschäftigt sich mit der sicheren Übertragung von Patienteninformationen von einer mobilen Einheit zu einem Server zum Zwecke des Trackings von Hörscreenings. Hierzu wird das Messgerät an ein Funkmodul angeschlossen, wodurch eine Verbindung zum Server aufgeabut werden kann. Da es sich hierbei um empfindliche Daten handelt, nimmt die Sicherheit des Kommunikationskanals eine wesentliche Rolle ein. Neben dieser werden noch andere Anforderungen an die Systemkomponenten gestellt, die eingehalten sind.

Abstract:

As mobile phones are starting to get equipped with inertial sensors, indoor navigation for pedestrians becomes an increasingly interesting topic in research. This work aims to develop and evaluate the use of a Particle Filter to deal with noisy sensor measurements of an Inertial Measurement Unit (IMU) providing localization and tracking of a pedestrian in indoor environments. Designed at the Institute for Real-Time Computer Systems (RCS), the so called Inav-System was used, which can extract the motion of a person from inertial sensor measurements. On this basis a Particle Filter was implemented, which uses Dead Reckoning in combination with a geometric floor plan to localize and track a person wea- ring the Inav-System in a building. In addition the concept of the Accessibility Map (AM) is proposed which reflects human walking preferences in the degree of accessibility of space in a floor and which makes it possible to exploit this information in the designed Particle Filter. Reinterpreting the AM as a Radial Basis Function Network, a special type of Neural Network, a method for learning accessibility of space in a floor is derived. Measurements show that the additional use of the AM in the Particle Filter yields an improvement in the localization accu- racy of up to 32%, resulting in an average accuracy of up to 1.1m. Deploying the AM and the learning AM, also a more robust tracking could be observed.This means besides the ability to monitor the walking patterns of a pedestrian in a building with a Particle Filter, the localization accuracy and the tracing robustness could be enhanced by the proposed AM.

Abstract:

The disk and the DRAM in a typical mobile system consume a significant fraction (up to 30%) of the total system energy. To save on storage energy, the DRAM should be small and the disk should be spun down for long periods of time. We show that this can be achieved for predominantly streaming workloads by connecting the disk to the DRAM via a large non-volatile memory (NVM). We refer to this as the NVM-based architecture (NVMBA); the conventional architecture with only a DRAM and a disk is referred to as DRAMBA. The NVM in the NVMBA acts as a traffic reshaper from the disk to the DRAM. If the cost increase due to adding the NVM is compensated by the decrease in DRAM cost, the total system cost may remain the same.

We analyze the energy saving of NVMBA, with flash serving as NVM, relative to DRAMBA with respect to (1) the streaming demand, (2) the disk form factor, (3) the best-effort percentage, and (4) the stream position on the disk. We present a worst-case analysis of the reliability of the disk drive and the flash memory and show that a small flash capacity is sufficient to operate the system over a year at negligible cost. Disk lifetime is superior to flash, so that it is not a concern.

Biography:

Mohammed G. Khatib is a postdoctoral researcher at the University of Twente in the Netherlands. He received his MSc degree in Computer Science from the Technical University of Braunschweig in Germany in 2004 and the PhD degree in Computer Science from the University of Twente in 2009. Dr. Khatib's research interests revolve around Green Computing. He investigates energy-efficient computer architecture and storage systems. He was a visiting scholar at the SSRC center at the University of California at Santa Cruz from January 2008 through May 2008. He is a program committee and the publication chair of IEEE MSST 2010. He served as a reviewer for ACM TECS 2010 ESTIMedia special edition and IEEE RTAS WiP 2010.

Abstract:

Distributed real-time systems implemented networked applications with timeliness requirements. Such systems must deliver correct values over a network within bounded time.

In this talk, I will present an overview of my work on state-based communication scheduling. State-based communication schedules permit designing systems for the worst case but executing the best case as state-based schedules are a powerful, expressive mechanism to program adaptive but still verifiable communication behavior. I will introduce the underlying concepts, touch on topics such as schedule generation, verification, and implementation at line speed, and show a case study on medical device interoperability. I will finish with lessons learnt from over six years working on this topic and challenges ahead.

Biography:

Sebastian Fischmeister is currently Assistant Professor at the Department of Electrical and Computer Engineering at the University of Waterloo, Canada. He received his MASc in Computer Science at the Vienna University of Technology, Austria, and his Ph.D. degree at the University of Salzburg, Austria. He was subsequently awarded the APART stipend for young, execellent researchers in 2005 and worked at the University of Pennsylvania, USA, as Post Graduate Research Associate until 2008.

He performs systems research at the intersection of software technology, distributed systems, and formal methods. His preferred application areas are distributed embedded real-time systems in the domain of automotive systems and medical devices. He is now working on the theory and application of state-based schedules for adaptive systems and a debugging/tracing framework for time-sensitive systems.

Abstract:

We consider a network of controllers that observe and control a plant whose state space is determined by a set of continuous variables. We assume that at any instant, these variables are evolving at (different) constant rates. Each controller can switch the rates of a designated subset of the continuous variables; its 'write' variables. These mode changes are determined by the current values of a designated subset of the variables that a controller can observe; its 'read' variables. We require the 'write' variables to be exclusive while the 'read' variables may be shared.

We study the discrete time behavior of such systems modeled as a network of hybrid automata. We show that the set of global control state sequences displayed by the network is regular. More importantly, we show that one can effectively and succinctly represent this regular language as a product of local finite state automata.

Biography:

P.S. Thiagarajan is a Professor in the Department of Computer Science and is the Vice Dean (Research) in the School of Computing, NUS. He is also a Senior Faculty Member of the NUS Graduate School of Integrative Science and Engineering (NGS). He received a B.Tech (Electronics) degree from the Indian Institute of Technology, Madras, India (1970) and a PhD degree (Computer Science) from Rice University, Houston, Texas, USA (1972). He has been a Research Associate at MIT, a Research Scientist at GMD, St. Augustin, Germany, an Associate Professor in the CS Dept. of Aarhus University, an Associate Professor at the Institute of Mathematical Science, Chennai, India and a founding professor of the Chennai Mathematical Institute, Chennai, India.

Starting with Petri nets, he has extensively studied various aspects of the theory of distributed systems. Since moving to NUS, he has focused on real time, hybrid and embedded computing systems. In the last few years, computational systems biology has become his main field of research. He is a Fellow of the Indian Academy of Sciences and a Fellow of the Indian National Academy of Sciences and has served on the Governing Council of the European association for Theoretical Computer Science. He is currently a member of the Governing Council of the Chennai Mathematical Institute.

Abstract:

Bei der Tieto Deutschland GmbH wird derzeit, im Rahmen eines Vorfeldprojekts, ein Demonstrator für ein Kommunikationssystem entwickelt, der auf dem offenen Standard Ethernet Powerlink basiert. Dieser Demonstrator soll nun um eine weitere Komponente erweitert werden, die auf dem Funkstandard IEEE 802.15.4 basiert. In dieser Arbeit wird ein Übergang entwickelt, der den Datenaustausch zwischen Ethernet Powerlink-Netzwerk und dem Funknetzwerk bewerkstelligt. Das Zeitverhalten des Übergangs und des Gesamtsystems wird messtechnisch untersucht. Die Funktionalität wird abschließend anhand eines Motors, der an das Funknetz angeschlossen ist, veranschaulicht.

Abstract:

Model-based safety analysis of systems is an emerging trend in systems engineering. It comes on the heels of adoption of model-based approaches by industry for system development with considerable success. The distinguishing feature of this trend is the use of high-level models to capture aspects of system design in order to enable automated analysis for safety assessment. Several approaches have been proposed in the recent literature to shape this trend. They differ in the types of models used, the analyses supported and their rigor. One interesting development here is the renewed interest in the application of formal methods to provide a precise semantics to the models in play and analyze them with guarantees of soundness. Model checking, an analysis technique that has found much success in hardware and software verification, has received particular attention in this regard. In this talk, we review the concepts and artefacts used in safety analysis, followed by a discussion of our work (in progress) that is focused on model-based safety analysis for timed systems.

Biography:

K.C. Shashidhar is a researcher in the area of applied formal methods for systems and software engineering, with over 10 years of experience working for research institutes and corporate laboratories. At present, he is a recipient of the ERCIM 'Alain Bensoussan' Fellowship hosted by Fraunhofer Institute for Experimental Software Engineering (IESE) in Kaiserslautern, Germany. He has received his PhD from Katholieke Universiteit Leuven, Belgium, MTech from Indian Institute of Technology - Delhi and BEng from University of Mysore, India, all in Computer Science.

Abstract:

An admission control test is responsible for deciding whether a new task may be accepted by a set of running tasks, such that the already admitted and the new task are all schedulable. Admission control decisions have to be taken on-line and, hence, there is a strong interest in developing efficient algorithms for different setups. In this paper, we propose a novel constant-time admission control test for tasks scheduled on identical processors under partitioned Earliest Deadline First (EDF), i.e., once tasks have been assigned to a processor they remain on that processor. In particular, to model demanding real-time systems, we consider the case where relative deadlines may be less than the minimum separation between two consecutive task activations or jobs. The main advantage of the proposed test is that the time it takes is independent of the number of tasks currently admitted in the system. While it is possible to adapt polynomial-time schedulability tests from the literature to design a linear or even constant-time admission control for this setup, the test we propose provides a better accuracy/complexity ratio. We evaluate this test through a set of detailed experiments based on synthetic tasks and a realistic case study consisting of a real-time multimedia server.

Abstract:

Embedded control systems typically consist of several control loops, with different parts of each control application being mapped onto different processors that communicate over one or more communication buses. In such setups, the system architecture and scheduling policies have a significant impact on control performance. In this paper we show how to optimally choose the parameters of hierarchical schedules on the commu- nication bus in order to improve multiple control performance metrics.

Abstract:

Die zunehmenden Auswirkungen des Klimawandels erfordern eine effiziente und nachhaltige Begrenzung der Auswirkungen der Luftfahrt auf die Umwelt. Im Gegensatz dazu stehen die prognostizierten langfristig stark ansteigenden Passagierzahlen. Um sowohl der erhöhten Transportleistung als auch den umweltpolitischen Zielen gerecht werden zu können, müssen neue Technologien für das Design und die Herstellung von Flugzeugstrukturen entwickelt werden. Dabei fällt ein großer Anteil auf faserverstärkte Kunststoffe, die jedoch noch nicht in großen Stückzahlen rationell zu verarbeiten sind.

Diese Arbeit ist Teil eines LUFO-IV Projektes namens ProFIT. In dem Förderprojekt soll eine automatisierte intelligente Tow Placement Anlage zur Ablage von endlosfaserverstärkten Halbzeugen in einer durchgängigen Prozesskette realisiert werden. Zur Ablage der Halbzeuge wird ein Industrieroboter eingesetzt der offline auf Grundlage von CAD-Daten programmiert werden soll. Zwischen den Faserhalbzeugen dürfen keine Lücken entstehen. Da verschiedene Ungenauigkeiten bei der Positionierung und durch die Werkzeugfertigung auftreten, müssen verschiedene Sensoren eingesetzt werden um diese auszugleichen und der Entstehung von Lücken entgegen zu wirken.

In dieser Arbeit wird ein Anlagenkonzept erstellt. Das Augenmerk wird dabei vor allem auf den Steuerungsrechner gerichtet. Der Rechner wird auf Linuxbasis arbeiten. Um den Echtzeitanforderungen des Industrieroboters nachzukommen wird das Betriebssystem mit RTAI erweitert. Zur Interprozesskommunikation wird Kogmo-RTDB eingesetzt und zur Ethernet-Kommunikation RTnet.

Abstract:

Execution-time analysis of real-time embedded software is an active area of research. In the past, a lot of the efforts in this area have been directed at analyzing sequential programs to give hard timing guarantees. At the National University of Singapore, we have built Chronos, a worst-case execution time (WCET) analyzer which performs detailed micro-architectural modeling. In this talk, I will briefly touch upon Chronos, and then focus on several other research activities which build on the Chronos effort. These include:

i) timing analysis of concurrent software on multi-cores (where the focus is on issues such as low-level thread interference and analyzing shared resources such as shared cache in multi-cores),

ii) timing analysis driven memory optimizations for both sequential and concurrent programs, and

iii) timing analysis of model-driven software (where the software is not hand-constructed but generated from high-level modeling languages).

Biography:

Abhik Roychoudhury is an Associate Professor of Computer Science at the National University of Singapore . Abhik received his Ph.D. in Computer Science from the State University of New York at Stony Brook . His research interests are in software and system validation with specific focus on embedded systems. Abhik has published widely in premier conferences and journals, with over 75 peer-reviewed publications. His research has led to scalable and usable analysis tools for embedded software which enhance software quality as well as programmer productivity. Two meaningful examples of such endeavor are the Chronos static analysis tool for ensuring time-predictable software execution, and the JSlice dynamic analysis tool for software debugging. Such tools have a substantial user-base spread across many different countries and have usage in teaching / development apart from research. His research has been recognized by various awards including ACM SIGSOFT Distinguished Paper Award (from ESEC-FSE 2009) and an IBM Faculty Award (2008).

Abstract:

Increasingly, stream processing applications include complex control structures to better adapt to changing conditions in their environment. This adaptivity often results in task execution rates that are dependent on the processed stream. Current approaches to compute buffer capacities that are sufficient to satisfy a throughput constraint have limited applicability in case of data-dependent task execution rates. This talk presents a dataflow model that allows tasks to have loops with an unbounded number of iterations. For instances of this dataflow model, we present efficient checks on their validity. Furthermore, we present an efficient algorithm to compute buffer capacities that are sufficient to satisfy a throughput constraint. This allows to guarantee satisfaction of a throughput constraint over different modes of a stream processing application, such as the synchronizing and synchronized modes of a digital radio receiver.

Biography:

Maarten Wiggers has M.S. ('04) and Ph.D. ('09) degrees in computer science from the University of Twente in The Netherlands. He is currently a postdoctoral researcher at the University of Twente in collaboration with and located at the University of California at Berkeley. His interests are in models and the corresponding analysis techniques to derive the temporal behavior of applications on predictable multi-processor systems.

Marco Bekooij obtained his Ph.D. degree from the Eindhoven University of Technology in 2004. He is currently a principal researcher at NXP Semiconductors and part-time full professor at the University of Twente. He is currently involved in the design of channel decoders for car radio and wireless LAN receivers. His current research interests include the design and analysis of predictable and composable embedded multiprocessor systems for stream processing applications and the development of multiprocessor compilers for real-time systems.

Abstract:

Echtzeitanforderungen sind essentiell für Applikationen im Industriebereich, wie z.B. Kontrollschleifen. Im Bereich der drahtlosen Sensornetze heißt dies, dass Übertragungsprotokolle und auch das Betriebssystem der Sensorknoten hart echtzeitfähig sein müssen.

Weit verbreitete Sensornetzbetriebssysteme wie z.B. TinyOS sind event-basierte Betriebssysteme, die auf einen geringen Energieverbrauch optimiert sind und ursprünglich nicht für den Einsatz in Echtzeitsystemen konzipiert sind. Aktuelle Erweiterungen von TinyOS integrieren allerdings nachträglich Echtzeitfähigkeit in das Betriebssystem, indem der bisherige nicht-präemptive Event-Scheduler durch einen prioritätsbasierten, präemptiven Scheduler ersetzt wurde. Dies hat weitreichende Folgen sowohl für den Compiler (einige Features funktionieren nicht mehr, z.B. der automatische Check für Race Conditions) als auch für das Task-Konzept (Registerinhalte müssen bei der Taskunterbrechung gespeichert werden). Welche Auswirkungen dies auf die Performance von TinyOS hat, ist ungeklärt. Ein alternativer Ansatz für ein echtzeitfähiges Sensornetzbetriebssystem ist z.B. FreeRTOS, das von Anfang an als Echtzeitbetriebssystem konzipiert wurde.

Die Vorteile von TinyOS liegen in seinem hohen Verbreitungsgrad, seine Energieeffizienz und das modulare Programmiermodell (NesC).Zudem gibt es eine große Auswahl an freier Software (z.B. Protokolle, Treiber), die einfach in neue Applikationen integriert werden kann. In dieser Diplomarbeit soll untersucht werden, ob TinyOS mit seiner erst nachträglich integrierten Echtzeitfähigkeit ähnliche Ergebnisse erzielen kann wie ein „reines“ Echtzeitbetriebssystem (FreeRTOS).

Ziele der Arbeit:
-Kurze Anforderungsanalyse von Industrieapplikationen bzgl. Sensornetze
-Portierung von FreeRTOS auf den ATMega1281
-Vergleich von TinyOS und FreeRTOS bzgl. der Echtzeitfähigkeit (Reaktionszeiten, Zuverlässigkeit) und Ressourcenverbrauch
-Entwicklung eines echtzeitfähigen Schedulers (z.B. Rate Monotonic)
-Entwicklung einer aussagekräftigen Testapplikation
-Bewertung der Einsatzfähigkeit Systeme in Industrieapplikationen

Abstract:

As semiconductor devices continue to scale down, process variations become more relevant for circuit design. Facing such variations, statistical static timing analysis is introduced to model variations more accurately so that the pessimism in traditional worst case timing analysis is reduced. Because all delays are modeled using correlated random variables, most statistical timing methods are much slower than the traditional corner-based timing analysis. To speed up statistical timing analysis, we propose methods to extract timing models for three common circuit types respectively. In order to use the extracted timing models in hierarchical designs, we propose a method to incorporate the correlation between modules by replacing independent random variables. This correlation strongly affects the delay distribution of the hierarchical design according to our experimental results. Because the extracted timing models are much smaller than the original circuits, timing analysis using them is much faster compared to previous approaches using flat netlists directly.;;Bing Li is from Institute for Electronic Design Automation, where he has been working toward the PhD degree since 2004. His research areas include statistical/static timing analysis and circuit optimization. He received his Bachelor and Master degrees from Beijing University of Posts and Telecommunications in 2000 and 2003 respectively.

Abstract:

Embedded Control Systems are growing in complexity with the increased use of electronics, and software in high-integrity application for automotive domains. They provide for enhanced safety, automation and comfort. These systems are distributed, fault-tolerant, real-time systems with hybrid (discrete and continuous) behaviour. Furthermore, many of the control functions, such as by-wire controls, have stringent quality and high-integrity requirements. The research community has been addressing these challenges, and over the last few years several design methodologies and tools for developing distributed embedded control systems have emerged. In spite of these, development of these applications remains a daunting task, requiring a great degree of human skill, expertise, time, and effort. It is imperative to invest significant R&D effort in coming up with methods and tools for future embedded control applications.

We believe that future methodologies will involve three key ingredients: comprehensive model-based development, math-based formal frameworks, component-oriented and product-line based development. In this talk we will describe all these aspects in the context of automotive software and discuss some of the recent efforts undertaken in our research lab. This includes a formal methods based timing analysis methodology and an early design space exploration of real-time bounds of Components in Distributed Embedded Systems.

Biography:

S. Ramesh has more than 20 years of research experience in the areas of high level language design, validation and verification of distributed and reactive systems. In these areas, he has published around 75 research papers in many international journals and conferences. He has been on the programme and review committees of many international conferences and journals. He has participated in a number of industrial sponsored and collaborative R&D projects.

Currently he holds the position of Technical Fellow at the India Science Labs., General Motors R&D, Bangalore, directing high quality research in the area of rigorous methods and tools for embedded software development. Prior to joining GM, he was on the faculty of Dept of Computer Science and Engineering, IIT Bombay for more than fifteen years. There he co-founded the Centre for Formal Design and Verification of Software IIT Bombay to develop tools and techniques for formal verification of industrial software and hardware systems.

His recent research interests are: Model Based and component-oriented approach to developement of distributed embedded control Software, use of formal methods in the rigorous development of industrial embedded software systems.

Abstract:

Improvements in lithography-based chip manufacturing technology have propelled an astonishing growth of electronic systems. However, serious challenges to this trend are due to fundamental physical limits of CMOS technology. Emerging nanotechnologies using bottom-up self-assembly fabrication promise to supersede and/or co-exist with CMOS technology in future.

A major challenge for emerging nanotechnologies is reliability. Due to inherent non-determinism in the bottom-up self-assembly fabrication processes of nanotechnologies, nano devices are orders of magnitude more fragile than those fabricated using conventional lithography. The result is an increased number of all types of failures that occur both at the manufacturing and during operating lifetime, as well as extreme parametric variations. In this talk, challenges for dependable nano computing will be discussed and efficient approaches for defect, fault and variation tolerance will be overviewed.

Biography:

Mehdi Tahoori is a full professor and Chair of Dependable Nano-Computing (CDNC) at the Department of Computer Science, Karlsruhe Institute of Technology (KIT), Germany. He is also an adjunct professor of Electrical and Computer Engineering at Northeastern University, Boston, USA. He received his PhD and M.S degrees in Electrical Engineering from Stanford University in 2003 and 2002, respectively, and a B.S. in Computer Engineering from Sharif University of Technology in Iran, in 2000. In 2003, he joined the Electrical and Computer Engineering Department at the Northeastern University as an assistant professor where he promoted to the rank of associate professor with tenure in 2009. During 2002 to 2003, he was a research scientist at Fujitsu Labs of America working on reliability issues in deep sub-micron VLSI designs. His research interests include nano computing, reliable computing, VLSI testing, reconfigurable computing, emerging nanotechnologies, and system biology. He was a recipient of National Science Foundation (NSF) Early Faculty Development (CAREER) award.

Abstract:

Bei diesem Projekt geht es um ein normales für den RC-Car Modellbau erhältliches Modellfahrzeug [1], welches für autonomes Fahren umgerüstet werden soll. Das Fahrzeug besteht im Wesentlichen aus einem ca. 45cm großen Aluminiumchassis, welches auf beiden Achsen von 2 Elektromotoren angetrieben und auf der Vorderachse von einem analog angesteuerten Servomotor gelenkt wird. Die weitere Elektronik auf der Fahrzeugplattform besteht aus einem Fahrtregler zur Steuerung der Elektromotoren und einem Empfänger, welcher die Steuersignale von der Fernbedienung empfängt, in PWM-Signale [2] umwandelt und an Servomotor und Fahrtregler überträgt.

Abstract:

Applications for parallel and distributed embedded systems are often specified as dataflow graphs with dependency cycles. Examples of corresponding models of computation are marked graphs or synchronous dataflow (SDF) graphs. Performance analysis is often used in the exploration of different implementation alternatives or in order to provide guarantees on the timing behavior. This paper describes a new approach to the modular performance analysis of cyclic dataflow graphs such as SDF graphs as existing component-based analysis methods are not able to faithfully deal with cycles in the event flow. The new method results in tight bounds on essential quantities like buffer sizes, end-to-end delays and throughput. Because of the generality of the approach, one can analyze not only systems that can be modeled as marked graphs but also implementations that contain buffers with finite sizes, that produce system-wide back-pressure caused by blocking write semantics. The embedding of the novel approach into a modular performance analysis method allows the analysis of distributed implementations that use resource sharing mechanisms such as fixed-priority scheduling and time division multiple access (TDMA). The paper presents the new models and methods as well as experimental results.

Biography:

Nikolay Stoimenov is a research assistant at the Computer Engineering and Networks Laboratory at ETH Zurich, Switzerland. His research interests lie in analytical methods for performance analysis of distributed embedded real-time systems. He has graduated with a Bachelor and a First class Honours degree in Computer Science, both from the University of Adelaide, Australia.

Abstract:

Echtzeitanforderungen sind essentiell für Applikationen im Industriebereich, wie z.B. Kontrollschleifen. Im Bereich der drahtlosen Sensornetze heißt dies, dass Übertragungsprotokolle und auch das Betriebssystem der Sensorknoten hart echtzeitfähig sein müssen.

Weit verbreitete Sensornetzbetriebssysteme wie z.B. TinyOS sind event-basierte Betriebssysteme, die auf einen geringen Energieverbrauch optimiert sind und ursprünglich nicht für den Einsatz in Echtzeitsystemen konzipiert sind. Aktuelle Erweiterungen von TinyOS integrieren allerdings nachträglich Echtzeitfähigkeit in das Betriebssystem, indem der bisherige nicht-präemptive Event-Scheduler durch einen prioritätsbasierten, präemptiven Scheduler ersetzt wurde. Dies hat weitreichende Folgen sowohl für den Compiler (einige Features funktionieren nicht mehr, z.B. der automatische Check für Race Conditions) als auch für das Task-Konzept (Registerinhalte müssen bei der Taskunterbrechung gespeichert werden). Welche Auswirkungen dies auf die Performance von TinyOS hat, ist ungeklärt. Ein alternativer Ansatz für ein echtzeitfähiges Sensornetzbetriebssystem ist z.B. FreeRTOS, das von Anfang an als Echtzeitbetriebssystem konzipiert wurde.

Die Vorteile von TinyOS liegen in seinem hohen Verbreitungsgrad, seine Energieeffizienz und das modulare Programmiermodell (NesC).Zudem gibt es eine große Auswahl an freier Software (z.B. Protokolle, Treiber), die einfach in neue Applikationen integriert werden kann. In dieser Diplomarbeit soll untersucht werden, ob TinyOS mit seiner erst nachträglich integrierten Echtzeitfähigkeit ähnliche Ergebnisse erzielen kann wie ein „reines“ Echtzeitbetriebssystem (FreeRTOS).

Ziele der Arbeit: - Kurze Anforderungsanalyse von Industrieapplikationen bzgl. Sensornetze

- Portierung von FreeRTOS auf den ATMega1281

- Vergleich von TinyOS und FreeRTOS bzgl. der Echtzeitfähigkeit (Reaktionszeiten, Zuverlässigkeit) und Ressourcenverbrauch

- Entwicklung eines echtzeitfähigen Schedulers (z.B. Rate Monotonic)

- Entwicklung einer aussagekräftigen Testapplikation

- Bewertung der Einsatzfähigkeit Systeme in Industrieapplikationen